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timing:vr04,
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xpress-book,
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timing:smo90,
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HLS:Latch06,
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      Year = {2006} }

@incollection{
PST:BOOK3,
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   Title = {Reducing the Timing Overhead},
   BookTitle = {Closing the Gap Between ASIC and Custom},
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      Year = {2007} }



@incollection{
PST:BOOKREPLACE,
   Author = {Chinnery, David and Keutzer, Kurt and Sanghavi, Jagesh and Killian, Earl and Sheth, Kaushik},
   Title = {Automatic Replacement of Flip-Flops by Latches in ASICs},
   BookTitle = {Closing the Gap Between ASIC and Custom},
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PST:CPC05,
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575-581},
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PST:WMD96,
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   Title = {Useful-skew clock routing with gate sizing for low power design},
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PST:SRI07,
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   Title = {Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation},
   BookTitle = {Proceedings of the 2007 international symposium on Physical design},
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11-18},
      Year = {2007} }

@inproceedings{Shiue2000,
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@misc{
URL:NCX,
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@BOOK{Bailey2007,
  title = {{ESL} Design and Verification: A Prescription for Electronic System
	Level Methodology},
  publisher = {Morgan Kaufmann/Elsevier},
  year = {2007},
  author = {Brian Bailey and Grant Martin and Andrew Piziali},
  owner = {cyber},
  timestamp = {2011.04.10}
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@INPROCEEDINGS{Cong2004,
  author = {Cong, J. and Jie Wei and Yan Zhang},
  title = {A thermal-driven floorplanning algorithm for 3D ICs},
  booktitle = {Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference
	on},
  year = {2004}
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@INPROCEEDINGS{Dong2009,
  author = {Xiangyu Dong and Yuan Xie},
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  booktitle = {Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC)},
  year = {2009},
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	Network Co-synthesis},
  booktitle = {Design Automation Conference (ASP-DAC), 2010 15th Asia and South
	Pacific},
  year = {2010}
}

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  author = {Sawicki, S. and Wilke, G. and Johann, M. and Reis, R.},
  title = {A cells and I/O pins partitioning refinement algorithm for 3D VLSI
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  booktitle = {Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International
	Conference on},
  year = {2009}
}

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@book{
HLS:newbook,
    author = {P. Coussy and A. Morawiec (Editors)},
    title = {High-Level Synthesis: From Algorithm to Digital Circuit },
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    year = {2009}
}

@inproceedings{UsamiI00,
  author    = {K. Usami and M. Igarashi},
  title     = {Low-power design methodology and applications utilizing
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  booktitle = {ASPDAC},
  year      = {2000},
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@inproceedings{Shin09,
  author    = {I. Shin and S. Paik and Y. Shin},
  title     = {Register allocation for high-level synthesis using dual supply voltages},
  booktitle = {DAC},
  year      = {2009},
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@inproceedings{
HLS:Ishihara04,
    author = {F. Ishihara and F. Sheikh and B. Nikolic},
    title = {Level conversion for dual-supply systems},
    booktitle = {IEEE TVLSI},
    year = {2004}
}


@ARTICLE{Davis2005,
  author = {Davis, W. R. and Wilson, J. and et al.},
  title = {Demystifying {3D ICs}: the pros and cons of going vertical},
  journal = {IEEE Design \& Test of Computers},
  year = {2005},
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@ARTICLE{Huang2006,
  author = {W. Huang and Ghosh, S. and et al.},
  title = {HotSpot: a compact thermal modeling methodology for early-stage {VLSI}
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@ARTICLE{Xie2006,
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@inproceedings{
KJLJ01,
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@inproceedings{
MV04,
   Author = {Madhubanti, Mukherjee and Ranga, Vemuri},
   Title = {Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems},
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@inproceedings{
SHSS03,
   Author = {Stammermann, A. and Helms, D. and Schulte, M. and Schulz, A. and Nebel, W.},
   Title = {Binding, Allocation and Floorplanning in Low Power High-Level Synthesis},
   BookTitle = {ICCAD},
      Year = {2003} }



@inproceedings{
KK07,
   Author = {Vyas, Krishnan and Srinivas, Katkoori},
   Title = {A {3D}-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits},
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@inproceedings{
GWDZ05,
   Author = {Zhenyu, Gu and Jia, Wang and \emph{et al}},
   Title = {Incremental exploration of the combined physical and behavioral design space},
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@inproceedings{Hung06,
	author = {Hung, W.-L. and Link, G. M. and \emph{et al}},
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@misc{
URL:IVM,
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@INPROCEEDINGS{Araki2010,
  author = {Araki, D.  and Nakamura, A.  and Miyama, M. },
  title = {Model-based {SoC} design using {ESL} environment},
  booktitle = {SOCC},
  year = {2010},
  __markedentry = {[yxc236]},
  doi = {10.1109/SOCDC.2010.5682968},
  owner = {yxc236},
  timestamp = {2011.04.14}
}

@INPROCEEDINGS{Schafer2010,
  author = {Schafer, B. C.  and Trambadia, A.  and Wakabayashi, K. },
  title = {Design of complex image processing systems in {ESL}},
  booktitle = {ASP-DAC},
  year = {2010},
  __markedentry = {[yxc236]},
  doi = {10.1109/ASPDAC.2010.5419780},
  owner = {yxc236},
  timestamp = {2011.04.14}
}

@INPROCEEDINGS{Su2010,
  author = {Su, A. P. },
  title = {Application of {ESL} Synthesis on {GSM} Edge algorithm for base station},
  booktitle = {ASP-DAC},
  year = {2010},
  __markedentry = {[yxc236]},
  doi = {10.1109/ASPDAC.2010.5419791},
  owner = {yxc236},
  timestamp = {2011.04.14}
}

@INPROCEEDINGS{Mercier2006,
  author = {Mercier, P. and Singh, S. R. and Iniewski, K. and Moore, B. and O'Shea,
	P. },
  title = {Yield and Cost Modeling for {3D} Chip Stack Technologies},
  booktitle = {CICC},
  year = {2006},
  doi = {10.1109/CICC.2006.320948}
}

@INPROCEEDINGS{Chen2010,
  author = {Yibo Chen and Dimin Niu and Yuan Xie and Chakrabarty, K.},
  title = {Cost-effective integration of three-dimensional {(3D) ICs} emphasizing
	testing cost analysis},
  booktitle = {ICCAD},
  year = {2010},
  pages = {471--476},
  doi = {10.1109/ICCAD.2010.5653753},
  owner = {yxc236},
  timestamp = {2011.04.14}
}
